Flash and other types of electronic memory devices are constructed of thousands or millions of memory cells, adapted to individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read, program, or erase operations through address decoding circuitry, whereby such operations may be performed on the cells within a specific byte or word. The individual memory cells are typically comprised of a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell MOS device, in an erase or program operation the voltages are applied so as to cause a charge to be stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access to other devices in a system in which the memory device is employed.
In single bit memory architectures, each cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The slacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
“Hot” (high energy) electrons in the channel near the drain can program a typical single bit type memory cell, which results from a relatively high voltage to the control gate and a moderately high voltage to the drain region. The hot electrons accelerate across the tunnel oxide and into the floating gate, which become trapped in the floating gate because of surrounding insulators. As a result of the trapped electrons, a threshold voltage of the memory cell increases. This change in the threshold voltage (and thereby the channel conductance) of the memory cell created by the trapped electrons is what causes the memory cell to be programmed.
To read the memory cell, a predetermined gate voltage greater than the threshold voltage of an unprogrammed memory cell, but less than the threshold voltage of a programmed memory cell, is applied to the gate. If the memory cell conducts (e.g., a sensed current in the cell exceeds a minimum value), then the memory cell has not been programmed (the memory cell is therefore at a first logic state, e.g., a one “1”). If, however, the memory cell does not conduct (e.g., the current through the cell does not exceed a threshold value), then the memory cell has been programmed (the memory cell is therefore at a second logic state, e.g., a zero “0”). Thus, each memory cell may be read in order to determine whether it has been programmed (and therefore identify the logic state of the data in the memory cell).
EEPROM memory, such as flash memory is a type of non-volatile electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 10 MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell.
More recently, flash memory devices have incorporated dual bit cell architectures, in which the core cells can each store two data bits. Dual bit memory cells are generally symmetrical, wherein the drain and source terminals are interchangeable. When appropriate voltages are applied to the gate, drain, and source terminals, one of the two bits may be accessed (e.g., for read, program, erase, verify, or other operations). When another set of terminal voltages are applied to the dual bit cell, the other of the two bits may be accessed.
Core cells in flash memory devices, whether single bit or multiple-bit, may be interconnected in a variety of different configurations. For instance, cells may be configured in a NOR configuration, with the control gates of the cells in a row individually connected to a wordline. In addition, the drains of the cells in a particular row are connected together by a conductive bitline. In the NOR configuration, each drain within a single column is connected to the same bitline. In addition, each flash cell associated with a given bitline has its gate coupled to a different wordline, while all the flash cells in the array have their source terminals coupled to a common source terminal, such as Vss or ground. In operation, individual flash cells in such a NOR configuration are addressed via the respective bitline and wordline using peripheral decoder and control circuitry for programming (writing), reading, erasing, or other functions.
Another cell configuration is known as a virtual ground architecture, in which the gates of the core cells in a row are tied to a common wordline. A typical virtual ground architecture comprises rows of flash memory core cell pairs with a drain of one cell transistor coupled to an associated bitline and the source of the adjacent core cell transistor. An individual flash cell is selected via the wordline and a pair of bitlines bounding the associated cell. For instance, such a cell may be read by applying voltages to the gate (e.g., via the common wordline) and to a bitline coupled to the drain, while the source is coupled to ground (Vss) via another bitline. A virtual ground is thus formed by selectively switching to ground the bitline associated with the source terminal of only those selected flash cells which are to be read. In this regard, where the core cells are of a dual bit type, the above connections can be used to read a first bit of the cell, whereas the other bit may be similarly read by grounding the bitline connected to the drain, and applying a voltage to the source terminal via the other bitline.
State of the art high performance flash memory devices, such as ORNAND/NOR/NAND devices can achieve a density substantially higher than the conventional EEPROM non-volatile memory and is suitable for the mass storage and code storage in commercial as well as consumer products. As modern day flash memory and other non-volatile memory demands smaller and smaller area while maintaining or increasing density, efficiently using die size is an increasingly more important issue than in the past. Although technology has been able to scale down the size of core cells significantly, neighboring decoding circuits cannot keep up with the scaling of the core arrays mainly due to the electrical properties of the core cell operation. As a result, these decoding circuits, also known as sector selects, greatly overpower the core cell in area thereby creating severe overhead in silicon area consumption and making down scaling highly inefficient. Additionally, as these sector selects are repeated throughout the die and occur as many times as sectors themselves, their overhead penalty is multiplied and even more severe. Hence, there is a need for improved methods and apparatus by which the adverse effects of the overhead penalty can be reduced or mitigated in flash memory devices.